Code converter and method for a data processing system

ABSTRACT

Disclosed is a method and apparatus for converting numbers in one base system to equivalent numbers in another base system. In one example, a binary number Nx is converted to a binary-codeddecimal (BCD) equivalent Bz. The method and apparatus employ a multiplier within the execution unit of the data processing system. The steps performed include first multiplying the binary number Nx which is within the range 0 to 10Y, by a binary factor approximately equal to 10 Y to form a first product Bz(0).Yx(0). Thereafter, Yx(0) is multiplied by binary 10 1 to form the product Bz(1).Yx(1). The iteration continues with each term Yx(i) multiplied by binary 10 1 to form each new product Bz(i+1).Yx(i+1) where the desired BCD number is Bz(0), Bz(1), . . . , Bz(i), Bz(i+1), . . . , Bz(n-1).

[ CODE CONVERTER AND METHOD FOR A DATA PROCESSING SYSTEM Inventors: GeneM. Amdhal, Saratoga; Michael R. Clements, Santa Clara, both of Calif.

Amdahl Corporation, Sunnydale, Calif.

22 Filed: Och-30,1972

21 Appl.No;:302,224

Assignee:

US. Cl. 235/155 Int. Cl. H03k 13/24 Primary E.taminerThomas A. RobinsonField of Search 340/1725; 235/154, 155' Apr. 9, 1974 ABSTRACT theproduct Bz( l )'Yx( l The iteration continues with each term Yx(i)multiplied by binary 10*1 to form each new product Bz(i+1)-Yx(i+l) wherethe desired BCD number is Bz(O), Bz(l),

Bz(i+l), Bz(nl). Attorney, Agent, or Frrm-Flehr, Hohbach, Test, Albutton& Herbert I 4 Claims, 3 Drawing Figures 2 4 6 v Mm 570.040! (MA/Na f 1.h 570.?! (Mi) (aw-e04 (5)] Vwrft) /0 A/srwcmw firm/flaw V/v/r. r1 z/Mr(5) CODE CONVERTER AND METHOD FOR A DATA PROCESSING SYSTEM CROSSREFERENCE TO RELATED APPLICATIONS tlOIl.

BACKGROUND OF THE INVENTION The present invention relates to the fieldof data processing systems and specifically to the field of methods andapparatus for converting numbers in one code to numbers in a differentcode. 7

Prior art data processing systems usually'include, within theirinstruction set, instructions which require information to be codeddifferently from the code employed internally within the data processingsystem. High speed data processing systems typically employ binary codesfor internal processing while encoding and decoding from the binary codein order to communicate with I/O devices.

Some prior art methods and apparatus for executing conversions from onecode to another have employed combinations of adders and otherfunctional units rather than employing a single dedicated conversionapparatus. While conversion devices or algorithms employing addersandother functional units have been successfully employed, it isdesirable to employ methods' and apparatus which make use of high speedmultipliers.

SUMMARY OF THE INVENTION The present invention is a method and apparatusfor converting numbers in one code to numbers in a different code in adata processing system.

Numbers Nx to the base x are converted to equivalent numbers Bz to thebase z. Nx is included in the range between and Each number lBz includesthe digits Bz(0), Bz(1),. .Bz(i), Bz(i+l) Bz(n-l) The conversion from Nxto B2 is carried out by the initial step of multiplying Nx by z to formthe product Bz(0)'Yx(0). The truncated product term Yx(0) is multipliedby z to form the product Bz( l )-Yx( l Thereafter, each term Yx(i) ismultiplied by 2* to form each new product Bz(i+l)-Yx(i+1).

In a specific example of the present invention, the data processingsystem is binary and therefore x equals 2 and the conversion is tobinary-coded-decimal and therefore 2 equals 10. i

The present invention achieves the object of converting one numbersystem (e.g. binary) to another number system (e.g. BCD) employing aniterative process of multiplication within the data processing system.

Additional objects and features of the invention will appear from thefollowing description in which the preferred embodiments of theinvention have been set forth in detail in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a block diagram of abasic environmental system suitable for employing the conversion methodand apparatus of the present invention.

FIG. 2 depicts a flow chart of the method and steps of the presentinvention.

FIG. 3 depicts a schematic representation of the data paths andapparatus associated with the execution unit of the system of FIG. 1which carries out the method steps of FIG. 2.

OVERALL SYSTEM In FIG. 1, a basic environmental processing system isshown which is suitable for employing the conversion method andapparatus of the present invention. Briefly, that system includes a mainstore 2, a storage control unit 4,'an instruction unit 8, an executionunit 10, a

channel unit 6 with associated 1/0, and a console 12. In

accordance with well known principles, the data processing system ofFIG. 1 operates under control of a stored program of instructions.Typically, instructions and the data upon which the instructions operateare introduced from the I/O equipment via the channel unit 6 through thestorage control unit 4 into the main store 2. From the main store 2,instructions are fetched by the instruction unit 8 through the storagecontrol 4, and are decoded to control the execution of instructions.Execution unit 10 executes instructions decoded in the instruction unit8 and operates upon data communicated to the execution unit from theappropriate places in the system.

EXECUTION UNIT In FIG. 3, the execution unitl0 of the system of FIG. 1is shown in further detail. The execution unit has a plurality offunctional units including a multiplier 19, an adder 18, a shifter 30, abyte adder 32 and a LUCK unit 20 for performing logical and comparisonoperations. Those functional units are typically implemented usingapparatus and techniques well known in the data processing field. Inaddition to the functional units, the execution unit 10 includes aplurality of registers which function to store, to ingate and to outgatedata from the various functional units in controlled steps pursuant toexecuting the programmed instructions of the data processing system ofFIG. 1. Specifically, those registers are an I register 22, a 1Hregister 24, a 1L register 28, a 2H register 25, a 2L register 29, a Bregister 23, a G register 36, an S register 35, a C register 37, an Aregister 39 and an R register 34.

Additionally, the E unit 10 also includes a control 27 which controls ina conventional manner the ingating, outgating and other timingassociated with execution unit 10.

CONVERSION METHOD A number Nx to the base x is converted to anequivalent number Bz to the base z. Typically, x is 2 representing thebinary number system and z is base 10 representing a binary codeddecimal system.

The number B2 is formed of a plurality of digits Bz(i) which consists ofBz(l), Bz(2) Bz(i), Bz(i+l) Bz(nl Each of the digits Bz(i) can be one ormore bits. For BCD, each digit is four binary bits or one hexadecimaldigit.

The number Nx is defined, in the data processing system, to be greaterthan or equal to 0 and less than or equal to z where z is the base towhich conversion is made and is some integer.

In the method of the present invention, a number Kx in the base x isequal to 2*". Further, a number Cx in the base x is equal to z.

The number Nx is multiplied by Kx forming the first digit Bz() andforming some remainder Yx(0) to the right of the marking point, as givenby the following equation:

( Z(0)'Yx(0) Eq. (I)

The remainder Y(0) is multiplied by the constant value Cx to form thenext digit Bz(l) and the remainder Yx(l) as follows:

The remainder Yx(1) is multiplied by the constant Cx toform.Bz(2)'Yx,(2) as follows:

cx) 11(1 1 Bz(2)-Yx(2) The iteration continues multiplying each newremainder Yx(i) by Cx to form each new result Bx(i+1- )-Yx(i+l) asindicated generally as follows:

( [Y(i) Bz(i-l-l )-Yx(i+1) The desired converted number Bz is Bz(0),Bz(l) Bz(i), Bz(i+l) Bz(n-l).

BINARY BINARY-C ODED-DECIMAL I CONVERSION In a specific example of theabove method, the base x is 2 so that Nx represents a binary number andthe base 1 is so that the number B2 is an equivalent binary codeddecimal number.

For the data processing system of FIG. 1, numbers Nx are typicallyrepresented within 32 binary bits so that the value of z is 10Accordingly, in the base at the value of Kx equals 10" in the base 10which in hexadecimal format is 44B82FA1. Similarly, the value of Cx inthe base x is 10 in the base 10 which is A in hexadecimal format. I

For a binary to binary-coded-decimal conversion in accordance with themethod discussed above, the number Nx is multiplied by 44B82FAl to formthe first digit Bz(0) and a remainder Yx(0). Thereafter, each remainderYx(i) is multiplied by'A which is the hexadecimal representation of 10in the base 10.

For a specific example of the method of the present inventionimplemented in a binary to binary-codeddecimal conversion the number Nxin hexadecimal format is 0000FA67. The binary coded decimal number Bxgiven in decimal format is 000064103. The steps employed to formthenumber Bx from-the number Nx I TABLE 1v sTEP 0 x) x) Bz(0)'Yx(0)0.0004337849E63C7 v Bz(0) =0 STEP 1 IMO) I ]'=-Bz(1)-Yx 1 v0.002A02C2E2C Yx( 1 0.002A02C2E2C sTEP 2 IYXU) (CX) Bz( )'Yx(Z) 131 2 0m2 =0.01A41B9CE STEP 3 =Bz(3) 'Yx(3) STEP 4 z(4)-Yx(4) m4) 0.A41AC954STEP 5 l (C Bz(5)-Yx(5) (5) 6:

1 (5) 0.690BDDD4 STEP 6 (Cx) =B z(6)Yx(6) 82(6) :4 Y m6 0.1A76A4D0 STEP7 l Z(7)'Yx(7) m7 O.D8A27020 sTEP 8 =Bz( )'Yx(8) Yx(8) 0.56586l40 STEP 9[Y (CI) Bz(9)'Yx(9) 01(9) =3 While the invention has been particularlyshown and described with reference to' a preferred embodiment thereof itwill be understood by those skilled in the art that the foregoing andother changes in form and details may be made therein without departingfrom the spirit and scope of the invention.

We claim:

1. In a data processing system having a number Nx in a number system tothe base at and having a plurality of functional units including amultiplier, an adder, a shifter, a logical comparator, a plurality ofregisters and control means for controlling the processing of operandsby said functional units, the improvement comprising,

means for gating said number Nx to said multiplier,

means for gating a number Kx to saidmultiplier for multiplication bysaid number Nx to form the product Bz(0)-Yx(0),

means for sequentially gating the truncated remainders Yx(i) to saidmultiplier, and

means for repeatedly gating a number Cx equal to z to said multiplierfor multiplication by said truncated remainders Yx(i) to iterativelyform the products Bz(i+l)-Yx(i+l) for all values of ibetween 0 and (n-12. In a data processing system having a binary number Nx in a numbersystem to the base x where x is 2 and where Nx is in the range between 0and and having a plurality of functional units including a multiplier,an adder, a shifter, a logical comparator, a plurality of registers andcontrol means for controlling the processing of operands by saidfunctional units,,the imprgg rnegt for representing Nx as abinary-codednumber B2 comprising,

means for gating said number Nx to said multiplier,

means for gating a number Kx, equal to 10 in the number system to thebase 1, to said multiplier for multiplication by said number Nx to formthe product Bz(0)'Yx(O), where Bz(0) is one digit ofBz and Yx(0) is themultiplication remainder after truncating Bz(0 means for sequentiallygating the truncated remainder Yx(0) and for gating subsequentremainders Yx(i) to said multiplier, and means for repeatedly gating anumber Cx equal 10 to said multiplier for multiplication by saidtruncated remainder lx(i) to iteratively form the products Bz(i+lYx(i+l) for all values ofi between 0 and (n-1) thereby forming Bz withthe digits 82(0), Bz(l) Bz(nl). 3. The system of claim 2 wherein each ofsaid digit Bz(i) is four bits and wherein n equals 8.

4. In a data'processing system having a number Nx in a number system tothe base x and having a plurality of functional units including a,multiplier, an adder, a

shifter, a logical comparator, a plurality of registers and controlmeans for controlling the processing of operands by said functionalunits, the improvement comprising,

register means for electrically storing a number Nx,

means for gating said stored number'Nx to said multiplier, registermeans for electrically storing a number Kx,

between 0 and (n1 P031050 UNl'll-Il) sun-1s lp-x'rlm'r-OFFICE.CER'ilFICA'lE OF CGRRECTION Iatent N0. 3 ,803 ,392 Dated April '9 1974lr'went fl Gene M. Amdahl and Micheal R. Clements It is certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as-shown below:

IN THE INVENTORS NAME:

Cancelthe name "Amdhal" and substitute therefor IN THE ASSIGNEE'SADDRESS:

Cancel the oity "Sunnydale" and substitute therefor --Sunnyvale-.

IN THE CLAIMS:

Claim 4, column 6, line 35, oancel "Bz (i+lYx.Yx(i+l) and substitutetherefor --Bz(i+l).Yx(i+l)-.

Signed and sealed this 15th day of October 1974,

(SEAL).

Attest:

McCOY M. GIBSON JR. c. MARSHALL DANN Attesting Officer, Commissioner ofPatents P011050 UNl'll'll) six-mes iA'l'l'lNT-OFF i r 1 r 1 w T r CER 1H ICA l in 01* CORREC IION Patent No. 3,803,392 Dated April 9, 1974 lr'wn fl Gene M. Amdahl and Michael R. Clements It is certified that errorappears in the above-identified patent and that said Letters Patent arehereby corrected as shown below:

IN THE INVENTORS' NAMEZ Cancel'the name "Amdhal" and snbstitut'etherefor -Amdahl.

IN THE ASSIGNEE'S ADDRESS:

Cancel the eity "Sunnydale" and substitute thexefor --Sunnyval'e-.

IN THE CLAIMS: 1

Claim 4, column 6, line 35, eancel "Bz (i+lYx.Yx(i+I) and substitutetherefor --Bz(i+l).Yx(i+l)-.

Signed and sealed this 15th day of October l974 (SEAL) Attest'.

MCCOY M.' GIBSON JR. c. MARSHALL DANN Attesting Officer Commiss ioner ofPatents

1. In a data processing system having a number Nx in a number system to the base x and having a plurality of functional units including a multiplier, an adder, a shifter, a logical comparator, a plurality of registers and control means for controlling the processing of operands by said functional units, the improvement comprising, means for gating said number Nx to said multiplier, means for gating a number Kx to said multiplier for multiplication by said number Nx to form the product Bz(0).Yx(0), means for sequentially gating the truncated remainders Yx(i) to said multiplier, and means for repeatedly gating a number Cx equal to z 1 to said multiplier for multiplication by said truncated remainders Yx(i) to iteratively form the products Bz(i+1).Yx(i+1) for all values of i between 0 and (n-1).
 2. In a data processing system having a binary number Nx in a number system to the base x where x is 2 and where Nx is in the range between 0 and 10 y and having a plurality of functional units including a multiplier, an adder, a shifter, a logical comparator, a plurality of registers and control means for controlling the processing of operands by said functional units, the improvement for representing Nx as a binary-coded-number B2 comprising, means for gating said number Nx to said multiplier, means for gating a number Kx, equal to 10 y in the number system to the base x, to said multiplier for multiplication by said number Nx to form the product Bz(0).Yx(0), where Bz(0) is one digit of Bz and Yx(0) is the multiplication remainder after truncating Bz(0), means for sequentially gating the truncated remainder Yx(0) and for gating subsequent remainders Yx(i) to said multiplier, and means for repeatedly gating a number Cx equal 10 to said multiplier for multiplication by said truncated remainder Yx(i) to iteratively form the products Bz(i+1). Yx(i+1) for all values of i between 0 and (n-1) thereby forming Bz with the digits Bz(0), Bz(1) , . . . , Bz(n-1).
 3. The system of claim 2 wherein each of said digit Bz(i) is four bits and wherein n equals
 8. 4. In a data processing system having a number Nx in a number system to the base x and having a plurality of functional units including a multiplier, an adder, a shifter, a logical comparator, a plurality of registers and control means for controlling the processing of operands by said functional units, the improvement coMprising, register means for electrically storing a number Nx, means for gating said stored number Nx to said multiplier, register means for electrically storing a number Kx, means for gating said stored number Kx to said multiplier for multiplication by said number Nx to form the product Bz(0).Yx(0), register means for electrically storing products from said multiplier, means for sequentially gating stored truncated remainders Yx(i) to said multiplier for all values of i between 0 and (n-1), register means for electrically storing a number Cx, and means for repeatedly gating said stored number Cx equal to z 1 to said multiplier for multiplication by said truncated remainders Yx(i) to iteratively form the products Bz(i+1Yx.Yx(i+1) for all values of i between 0 and (n-1). 